Digital processing technologies
We live in an analogue world, but more and more, digital processing is changing the ways in which we interact with and experience the world. Whether through satellite navigation or autonomous vehicles, augmented reality, or simply our smartphones, digital processing allows us to live our lives in a host of new ways.
Processing information in real or near-real-time demands significant processing capacity. Moore’s Law has had a major effect on our ability to access that capacity, and there are now also several processing technologies available for design engineers to choose from when deciding what is most appropriate for their project.
Among these processing technologies are traditional processors like Graphics Processing Units (GPU), but also less well-known systems like Programmable Logic (PL).
As you’ll learn in this article – co-created with Mouser Electronics – programmable Logic is undeniably less widely known and is generally considered to be challenging to work with when implementing solutions, but it also comes with a host of benefits.
Programmable Logic – the benefits
If PL is so challenging, why use it? Despite the obstacles it presents, Programmable Logic offers users the chance to put in place genuinely parallel implementations of algorithms and applications, leading to more deterministic and responsive solutions.
Because of its real-time capabilities in processing and responses, PL is especially useful in fields such as vision and signal processing and RADAR.
Historically, Programmable Logic devices have been available in two classes: Complex Programmable Logic Devices (CPLD) and Field Programmable Gate Arrays (FPGA).
While CPLDs offer a simple structure of registers and logic functions using a sea-of-gates architecture, FPGAs are more complex, often including dedicated hardware elements – block memory, digital signal processing, clock management, gigabit serial transceivers, or IO blocks.
How is an FPGA structured?
At its base, an FPGA basically involves a lookup table (LUT), registers, and flexible IO cell structures. The LUT allows logic equations to be implemented, and registers provide the storage required for sequential logic designs.
By putting these two elements – the LUT and registers – together, what is sometimes known as a logic slice is created. In the devices we currently use, these slices make it possible to implement combinatorial or sequential logic circuits including local distributed memory and – depending on configuration – the possibility of using the LUT as a shift register.
Usually, two slices are grouped within the FPGA device to construct a Configurable Logic Block (CLB). These are then interconnected to create the functionality required by using routing and switching matrices.
A hardware description language (HDL) is generally used in designing FPGAs – most often Verilog or VHDL.
The description these languages provide is at a much more basic level than traditional software languages would offer, simply describing the design’s register level transfer – for example, implementing state machines, counters, and so on.
Both VHDL and Verilog offer inbuilt support for the concept of concurrency – essential if you want to model the FGPA’s parallel architecture.
By embedding IO structures in FPGA devices, a direct interface with a range of IO standards is made possible. The standards available to designers run the gamut from single-ended standards – LVCMOS – to differential standards like LVDS and TMDS. However, the technology’s capacity to interface doesn’t end there.
IO structures can provide on-chip termination, precise PS delays, and serializer/deserializers. This expands the range of FPGAs, which can interact with an unlimited range of both current and historic interfaces.
This extraordinary flexibility also means that system designers using Application Specific Standard Products (ASSP) can avoid becoming pin bound.
There are several stages necessary when creating a programmable logic design solution:
- Synthesis – The HDL design is turned into a series of logic equations and mapped onto the resources on offer in the FPGA.
- Place – The logic resources the synthesis tool has defined as necessary are located in the FPGA’s available spaces.
- Routing – The logic resources implanted in the design establish interconnectivity, using routing and switch matrices to implement the final application.
- Bit File – The final programming file for the target FPGA is generated.
To be certain that the design has implemented the functions required, a simulation is employed. Engineers use test benches to simulate inputs and monitor the related outputs in the register-transfer level (RTL) module.
Module behaviour can be checked by inspecting the waveform generated by the simulation, or, if the user feels like a challenge, by writing a more complex test bench that can verify outputs.
Despite the major performance and interfacing benefits of using an FPGA, the development process for solutions using this technology is often thought to be more complex than traditional software development.
However, those who view the development process in this way are overlooking the abilities of today’s devices, the broad availability of IP, and the assistance provided by the design tools now in use, such as high-level synthesis.
Types of FPGA devices
In 1985, Ross Freeman and Bernard Vonderschmitt released the XC2064, with a mere 64 configurable logic blocks.
Compare the first FPGA with the largest Xilinx devices in use now, with their 8,938,000 system logic cells, 76 Mb of Block RAM, 90 Mb of UltraRAM and 3840 DSP elements – FPGAs have come a long way in a relatively short time!
The Xilinx FPGA described above is the largest of its kind, and for many applications, would be far too powerful.
For projects that don’t need quite so much capacity, Xilinx offers a wide range of FPGA and System on Chip devices and can guide engineers in selecting the most appropriate option for their needs.
These devices belong to three different ‘families’ developed around the 28 nm node. These families are optimized for cost, and for specific users’ needs
- Spartan-7 FPGAs – following on from the widely-adopted Spartan-6 range, the Spartan-7 family delivers improved performance and requires less power than the old 45 nm node. I/O optimized, Spartan-7 devices have the highest pin count on offer in this portfolio.
- Artix-7 FPGAs – new to the Xilinx 7 series, Artix-7 FPGAs are transceiver-optimized, utilising 6.6 Gbps transceivers.
- Zynq-7000 SoCs – game-changing when they first appeared on the scene, the Zynq-7000 SoCs mixes Arm Cortex-A9 hardcore processors and the structure of an FPGA. This combination offers a new device class that opens the door to integrated system solutions. Add to this the benefits of integration, such as lower power consumption, a reduced solution footprint, and a major cut in EMI, and the Zynq-7000 SoCs remains revolutionary.
Applications ranging from sensor fusion to precision control, image processing, and cloud computing all find support in the devices included in this portfolio.
Top of the class
Beyond the options above, Xilinx offers the Kintex and Virtex families at 28nm, 20nm and 16nm technology nodes. Offering extreme performance and supporting more specialized applications, the UltraScale and UltraScale+ groups of devices bring weighty increases in performance and capability to the table.
The Kintex group of devices display increased performance, as well as more logic resources and transceivers across the three technology nodes.
Starting at 65,500 logic cells in the Kintex family, and rising to 1,143,000 cells in Kintex UltraScale+ devices, both offer support for data rates of up to 16.3 Gbps and 32.75 Gbps thanks to their GTH and GTY transceivers respectively.
The Virtex family of devices contains the highest-performing FPGAs. As well as supporting high bandwidth memory (HBM), Virtex devices have logic resources of up to 8.9 million system logic cells and transceivers able to operate at 58 Gbps
With between 4GB and 16GB of on-chip DRAM, and as much as 460 Gbps bandwidth – around 20 times higher than a DDR4 DIMM – the role of a Virtex HBM device is to speed up network and storage applications.
Toolchain
Xilinx development tools are available to support the smallest Spartan-7 to the largest Virtex UltraScale+. Every facet of the design process, from RTL capture to simulation and software development for use with processor cores, is incorporated in a comprehensive support package.
- Vivado Design Suite – Vivado allows the design to be captured and offers RTL simulation as well as facilitating an implementation process of synthesis, and place, route and bit file generation.
- Vivado HLS – IP development using C or C++ is enabled by high-level synthesis.
- Vitis Unified Software Platform – software development for embedded processors plus acceleration using OpenCL.
- PetaLinux Tools – a Linux solution for embedded processors.
From synthesis to simulation and beyond, and especially in the realm of verification tools, there are inevitably many other commercial and open-source software tools available for use in an FPGA development flow. However, our focus is the Xilinx range and what their FPGAs have to offer.
We will explore that subject in depth, looking at embedded processing, internal and external interfacing, design tools, and application focus, over a series of articles.
If you want more technical information about the hardware you can use for your project visit Mouser website.
